To make it possible for a semiconductor device to be operated at a high speed, fast charging/discharging of the capacitive load is required. Especially, in a conventional output buffer circuit (FIG. 1) of a memory device which is provided with numerous input/output terminals, a large value of di/dt is accompanied during the concurrent transitions of input/output data. Such a large value of di/dt causes noise both in the power line and the ground line to be produced. Further, as the power source voltage becomes higher and the temperature is lowered, the noise is increased.
This will adversely affect the TTL compatible input buffer, resulting in the chips becoming liable to give faulty operations, noise-sensitive circuitries such as sense amplifiers and the like also becoming liable to malfunction.
In an effort to give solution to the said problems, a circuit as shown in FIG. 2 was proposed. That is, as described in "A 21ns 32K.times.8 CMOS Static RAM With A Selectively Pumped p-Well Array," IEEE Journal of Solid-State Circuits. Vol. SC-22, No. 5 (Oct. 1987), an active resistance is inserted into the inverter located upstream of the output driver, as a means for reducing the noise in the output buffer. In such a device, some noise reductions may be obtained by inserting resistances R1-R4 into the source of the p-channel MOS pull-up device and into the source of the n-channel MOS pull-down device. However, in such a device, adverse effects are produced such that the access time, i.e., the operation speed becomes slow in the overall evaluation.